K4N26323AE Просмотр технического описания (PDF) - Samsung

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K4N26323AE

128Mbit GDDR2 SDRAM 1M x 32Bit x 4 Banks with Differential Data Strobe and DLL GDDR2 SDRAM

Samsung 

K4N26323AE-GC

128M GDDR2 SDRAM

Burst Read Operation Followed by Precharge: RL = 8 (AL=1, CL=7, tRP =8)

0

3

7

8

9

10

11

12

13

CK, CK

CMD

Posted CAS

READ A

Precharge A

NOP

NOP

NOP

NOP

Bank A

Activate

NOP

NOP

DQS

DQ’s

RL = 8

> = tRP

DOUTA0 DOUTA1 DOUTA2 DOUTA3

Burst Write followed by Precharge

For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command

can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the

precharge command. No Precharge command should be issued prior to the tWR delay, as GDDR2 SDRAM does not sup-

port any burst interrupt operation.

Burst Write followed by Precharge: AL = 1, CL = 7, WL = AL + 1 = 2, tWR = 5

0

1

2

3

4

5

6

9

CK, CK

CMD Posted CAS

WRITE A

NOP

DQS

DQ’s

WL = 2

NOP

NOP

NOP

DINA0 DINA1 DINA2 DINA3

NOP

NOP

NOP

Precharge A

tWR = 5

- 21 -

Rev. 1.7 (Jan. 2003)

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