ICS83940DYILFT Просмотр технического описания (PDF) - Renesas Electronics

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производитель

ICS83940DYILFT

Low Skew, 1 to 18 LVPECL to LVCMOS/LVTTL Fanout Buffer

Renesas Electronics 

ICS83940DI Datasheet

Table 5C. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C

Symbol Parameter

Test Conditions

fMAX

tPLH

Output Frequency

Propagation

Delay

Propagation

Delay

PCLK, nPCLK; NOTE 1, 5

LVCMOS_CLK; NOTE 2, 5

PCLK, nPCLK; NOTE 1, 5

LVCMOS_CLK; NOTE 2, 5

ƒ  150MHz

ƒ  150MHz

ƒ > 150MHz

ƒ > 150MHz

tsk(o)

Output Skew;

NOTE 3, 5

PCLK, nPCLK

LVCMOS_CLK

Part-to-Part Skew; PCLK, nPCLK

NOTE 6

LVCMOS_CLK

Measured on the Rising

Edge

at VDDO/2

ƒ  150MHz

ƒ  150MHz

tsk(pp)

Part-to-Part Skew; PCLK, nPCLK

NOTE 6

LVCMOS_CLK

ƒ > 150MHz

ƒ > 150MHz

tR / tF

odc

Part-to-Part Skew; PCLK, nPCLK

NOTE 4, 5

LVCMOS_CLK

Output Rise/Fall Time

Output Duty Cycle

Measured on the Rising

Edge

at VDDO/2

0.5V to 1.8V

ƒ < 166MHz

Minimum

1.2

1.5

1.5

2.0

0.3

40

Typical

Maximum

200

3.8

3.2

3.7

3.6

200

200

2.6

1.7

2.2

1.7

1.2

1.0

1.2

60

Units

MHz

ns

ns

ns

ns

ps

ps

ns

ns

ns

ns

ns

ns

ns

%

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the

device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after

thermal equilibrium has been reached under these conditions.

NOTE: All parameters measured at 200MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the output VDDO/2.

NOTE 2: Measured from VDD/2 to VDDO/2.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal

load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.

NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions.

Using the same type of inputs on each device, the outputs are measured at VDDO/2.

©2020 Renesas Electronics Corporation

8

January 7, 2020

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