IDT72V3622L15PFG Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

производитель

IDT72V3622L15PFG

3.3 VOLT CMOS SyncBiFIFO™ 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

tENS2

tENH

ENB

CLKA

AEA

tSKEW2(1)

1

X2 Words in FIFO2

2

tPAE

tPAE

(X2+1) Words in FIFO2

tENS2

tENH

ENA

4660 drw 19

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising

CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

Figure 17. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)

CLKA

ENA

AFA

tENS2

tENH

tPAF

[D-(Y1+1)] Words in FIFO1

tSKEW2(1)

1

(D-Y1) Words in FIFO1

2

tPAF

CLKB

tENS2

tENH

ENB

4660 drw 20

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising

CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT72V3622, 512 for the IDT72V3632, 1,024 for the IDT72V3642.

Figure 18. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)

25

Share Link: