ISL6415 Просмотр технического описания (PDF) - Renesas Electronics

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ISL6415

Triple Output Regulator with Single Synchronous Buck and Dual LDO

Renesas Electronics 

ISL6415

Pin Descriptions

PVCC - Positive supply for the power (internal FET) stage of

the PWM section.

SGND - Analog ground for the PWM. All internal control

circuits are referenced to this pin.

EN _PWM- The PWM controller is enabled when this pin is

HIGH, and held off when the pin is pulled LOW. It is a CMOS

logic-level input (referenced to VIN).

VIN_LDO - This is the input voltage pin for LDO1 and LDO2.

EN_LDO - LDO1 and LDO2 are enabled when this pin is

HIGH, and held off when the pin is pulled LOW. It is a CMOS

logic-level input (referenced to VIN).

CT - Timing capacitor connection to set the 25ms minimum

pulse width for the RESET/RESET signal.

RESET, RESET - These complementary pins are the

outputs of the reset supervisory circuit, which monitors VIN.

The IC asserts these RESET and RESET signals whenever

the supply voltage drops below a preset threshold; keeping

them asserted for at least 25ms after VCC (VIN) has risen

above the reset threshold. These outputs are push-pull.

RESET is LOW when re-setting the microprocessor. The

device will continue to operate until VIN drops below the

UVLO threshold.

PG_LDO - This is a high impedance open drain output that

provides the status of both LDO’s. When either of the

outputs are out of regulation, PG_LDO goes LOW.

CC1 - This is the compensation capacitor connection for

LDO1. Connect a 0.033µF capacitor from CC1 to

GND_LDO.

CC2 - This is the compensation capacitor connection for

LDO2. Connect a 0.033µF capacitor from CC2 to

GND_LDO.

VOUT2 - This pin is the output of LDO2. Bypass with a

2.2µF, low ESR capacitor to GND_LDO for stable operation.

GND_LDO - Ground pin for LDO1 and LDO2.

VOUT1 - This pin is the output of LDO1. Bypass with a

2.2µF, low ESR capacitor to GND_LDO for stable operation.

PGND - Power ground for the PWM controller stage.

VOUT - This I/O pin senses the output voltage of the PWM

converter stage. For fixed 1.2V operation, connect this pin

directly to the output voltage.

PG_PWM - This pin is an active pull-up/pull-down able to

source/sink 1mA (min.) at 0.4V from VIN/SGND. This output

is HIGH when VOUT is within ±8% (typ.).

PG_PWM - This pin provides an inverted PG_PWM output.

LX - The LX pin is the switching node of synchronous buck

converter, connected internally at the junction point of the

upper MOSFET source and lower MOSFET drain. Connect

this pin to the output inductor.

VIN - This pin is the power supply for the PWM controller

stage and must be closely decoupled to ground.

SYNC - This is the external clock synchronization input. The

device can be synchronized to 500kHz to 1MHz switching

frequency.

GND - Tie this pin to the ground plane with a low impedance,

shortest possible path.

FN9145 Rev 0.00

Dec 27, 2004

Page 8 of 13

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