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ISL6415

Triple Output Regulator with Single Synchronous Buck and Dual LDO

Renesas Electronics 

ISL6415

Functional Description

The ISL6415 is a 3-in-1 multi-output regulator designed for

wireless chipset power applications. The device integrates a

single synchronous buck regulator with dual LDOs. It

supplies three fixed output voltages 1.2V, 1.8V and 1.8V.

The 1.2V is generated using a synchronous buck regulator

with greater then 92% efficiency. Both 2.84V supplies are

generated from ultra low noise LDO Regulators.

Undervoltage lock-out (UVLO) prevents the converter from

turning on when the input voltage is less then typically 2.6V

Additional blocks include an output overcurrent protections,

thermal sensor, PGOOD detectors, RESET function and

shutdown logic.

Synchronous Buck Regulator

The synchronous buck regulator with integrated N- and P-

channel power MOSFET provides pre-set 1.2V for

BBP/MAC core supply. Synchronous rectification with

internal MOSFETs is used to achieve higher efficiency and

reduced number of external components. Operating

frequency is typically 750kHz allowing the use of smaller

inductor and capacitor values. The device can be

synchronized to an external clock signal in the range of

500kHz to 1MHz. The PG_PWM output indicates loss of

regulation on PWM output.

The PWM architecture uses a peak current mode control

scheme with internal slope compensation. At the beginning

of each clock cycle, the high side P-channel MOSFET is

turned on. The current in the inductor ramps up and is

sensed via an internal circuit. The error amplifier sets the

threshold for the PWM comparator. The high side switch is

turned off when the sensed inductor current reaches this

threshold. After a minimum dead time preventing shoot

through current, the low side N-channel MOSFET will be

turned on and the current ramps down again. As the clock

cycle is completed, the low side switch will be turned off and

the next clock cycle starts.

The control loop is internally compensated reducing the

amount of external components. The PWM section includes

an anti-ringing switch to reduce noise at light loads.

The switch current is internally sensed and the minimum

current limit is 600mA.

Synchronization

The typical operating frequency for the converter is 750kHz

if no clock signal is applied to the SYNC pin. It is possible to

synchronize the converter to an external clock within a

frequency range from 500kHz to 1000kHz. The device

automatically detects the rising edge of the first clock and

will synchronize immediately to the external clock. If the

clock signal is stopped, the converter automatically switches

back to the internal clock and continues operation without

interruption. The switch over will be initiated if no rising edge

FN9145 Rev 0.00

Dec 27, 2004

on the SYNC pin is detected for a duration of two internal

1.3s clock cycles.

Soft-Start

As the EN_PWM (Enable) pin goes high, the soft-start

function will generate an internal voltage ramp. This causes

the startup current to slowly rise preventing output voltage

overshoot and high inrush currents. The soft-start duration is

typically 5.5ms with 750kHz switching frequency. When the

soft-start is completed, the error amplifier will be connected

directly to the internal voltage reference. The SYNC input is

ignored during soft-start.

Enable PWM

Logic low on EN_PWM pin forces the PWM section into

shutdown. In shutdown, all the major blocks of the PWM

including power switches, drivers, voltage reference, and

oscillator are turned off.

Power Good (PG_PWM)

When the chip is enabled, this output is HIGH, when Vout is

within 8% of 1.8V and active low outside this range. When

the PWM is disabled, the output is active low. PG_PWM is

the complement of PG_PWM.

Leave the PG_PWM pin unconnected when not used.

PWM Overvoltage and Overcurrent Protection

The PWM output current is sampled at the end of each PWM

cycle. Should it exceed the overcurrent limit, a 4 bit up/down

counter counts up two LSB. Should it not be in overcurrent

the counter counts down one LSB (but counter will not

"rollover" or count below 0000). If >33% of the PWM cycles

go into overcurrent, the counter rapidly reaches count 1111

and the PWM output is shut down and the soft-start counter

is reset. After 16 clocks the PWM output is enabled and the

SS cycle is started.

If Vout exceeds the overvoltage limit for 32 consecutive clock

cycles the PWM output is shut off and the SS counters reset.

The soft-start cycle will not be started until EN or VIN are

toggled.

PG_LDO

PG_LDO is an open drain pulldown NMOS output that will

sink 1mA at 0.4V max. It goes to the active low state if either

LDO output is out of regulation by more than 15%. When the

LDO is disabled, the output is active low.

LDO Regulators

Each LDO consists of a 1.184V reference, error amplifier,

MOSFET driver, P-Channel pass transistor, dual-mode

comparator and internal feedback voltage divider.

The 1.2V band gap reference is connected to the error

amplifier’s inverting input. The error amplifier compares this

reference to the selected feedback voltage and amplifies the

difference. The MOSFET driver reads the error signal and

applies the appropriate drive to the P-Channel pass

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