ISL6446A Просмотр технического описания (PDF) - Renesas Electronics

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ISL6446A

Dual (180°Out-of-Phase) PWM and Linear Controller

Renesas Electronics 

ISL6446A

Figure 29 shows the circuit traces that require additional layout

consideration. Use single point and ground plane construction for

the circuits shown. Locate the RT resistor as close as possible to

the RT pin and the SGND pin. Provide a decoupling capacitor

CVCC between the VCC and PGND pins and place it as close to

VCC and PGND pins as possible shown in Figure 30.

FIGURE 30. CVCC PLACEMENT RECOMMENDATION

For each switcher, minimize any leakage current paths on the

SS/EN pin and locate the capacitor, CSS close to the SS/EN pin

because the internal current source is only 30µA. All of the

compensation network components for each switcher should be

located near the associated COMP and FB pins. Locate the

capacitor, CBOOT as close as practical to the BOOT and PHASE

pins (but keep the noisy PHASE plane away from the IC (except

for the PHASE pin connection).

The OCSET circuits (see Figure 4 on page 6) should have a

separate trace from the upper FET to the OCSET R and C; that will

more accurately sense the VIN at the FET than just tying them to

the VIN plane. The OCSET R and C should be placed near the IC

pins.

FN8384 Rev 3.00

Aug 27, 2015

Page 20 of 22

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