PCA9511A
FEATURE SELECTION
FEATURE SELECTION CHART
Feature
idle detect
high−impedance SDA, SCL pins for VCC = 0 V
rise time accelerator circuitry on SDAn and SCLn
lines
rise time accelerator circuitry hardware disable pin
for lightly loaded systems
rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin
ready open−drain output
two VCC pins to support 5 V to 3.3 V level
translation with improved noise margins
1 V precharge on all SDA and SCL lines
92 mA current source on SCLIN and SDAIN for
PICMG applications
PCA9510A
Yes
Yes
Yes
In only
PCA9511A
Yes
Yes
Yes
Yes
Yes
PCA9512A
Yes
Yes
Yes
Yes
Yes
Yes
PCA9513A
Yes
Yes
Yes
Yes
Yes
Yes
PCA9514A
Yes
Yes
Yes
Yes
Yes
BLOCK DIAGRAM
Figure 1. Block Diagram of PCA9511A
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