ADF4360-8(Rev0) Просмотр технического описания (PDF) - Analog Devices

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ADF4360-8
(Rev.:Rev0)

Integrated Synthesizer and VCO

Analog Devices 

Lock Detect

MUXOUT can be programmed for one type of lock detect.

Digital lock detect is active high. When LDP in the R counter

latch is set to 0, digital lock detect is set high when the phase error

on three consecutive phase detector cycles is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns

phase error are required to set the lock detect. It stays set high

until a phase error of greater than 25 ns is detected on any

subsequent PD cycle.

INPUT SHIFT REGISTER

The ADF4360 family’s digital section includes a 24-bit input

shift register, a 14-bit R counter, and an 18-bit N counter

comprised of a 5-bit A counter and a 13-bit B counter. Data is

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. These are the two LSBs, DB1

and DB0, shown in Figure 2.

The truth table for these bits is shown in Table 5. Table 6 shows

a summary of how the latches are programmed. Note that the

test modes latch is used for factory testing and should not be

programmed by the user.

Table 5. C2 and C1 Truth Table

Control Bits

C2

C1

Data Latch

0

0

Control Latch

0

1

R Counter

1

0

N Counter (B)

1

1

Test Modes Latch

VCO

The VCO core in the ADF4360 family uses eight overlapping

bands, as shown in Figure 19, to allow a wide frequency range to

be covered without a large VCO sensitivity (KV) and resultant

poor phase noise and spurious performance.

ADF4360-8

The correct band is chosen automatically by the band select

logic at power-up or whenever the N counter latch is updated. It

is important that the correct write sequence be followed at

power-up. This sequence is

1. R counter latch

2. Control latch

3. N counter latch

During band select, which takes five PFD cycles, the VCO VTUNE

is disconnected from the output of the loop filter and connected

to an internal reference voltage.

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

80

85

90

95

100

105

110

115

FREQUENCY (MHz)

Figure 19. Frequency vs. VTUNE, ADF4360-8, L1 and L2 = 270 nH

The R counter output is used as the clock for the band select

logic and should not exceed 1 MHz. A programmable divider is

provided at the R counter input to allow division by 1, 2, 4, or 8

and is controlled by Bits BSC1 and BSC2 in the R counter latch.

Where the required PFD frequency exceeds 1 MHz, the divide

ratio should be set to allow enough time for correct band

selection.

After band selection, normal PLL action resumes. The value of

KV is determined by the value of inductors used (see the

Choosing the Correct Inductance Value section). The ADF4360

family contains linearization circuitry to minimize any variation

of the product of ICP and KV.

The operating current in the VCO core is programmable in four

steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by

Bits PC1 and PC2 in the control latch.

Rev. 0 | Page 11 of 24

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