SSM2161 Просмотр технического описания (PDF) - Analog Devices
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SSM2161 Datasheet PDF : 7 Pages
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SSM2160/SSM2161–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (VS = ؎5 V, AV = 0 dB, 0 dBu = 0.775 V rms, VIN = 0 dBu, fAUDIO = 1 kHz, fCLK = 250 kHz, RL = 10 k⍀,
–40؇C < TA < +85؇C, unless otherwise noted. Typical specifications apply at TA = +25؇C.)
Parameter
Conditions
Min Typ Max
Units
AUDIO PERFORMANCE
Noise
Headroom
Total Harmonic Distortion Plus Noise
Channel Separation
VIN = GND, 20 kHz Bandwidth
Clip Point = 1% THD+N
2nd and 3rd Harmonics Only
AV = 0 dB
AV = –10 dB
Any Channel to Another
–100
dBu
+10
dBu
0.008 TBD
%
0.02 TBD
%
80
dB
ANALOG INPUT
Input Offset Voltage
10
mV
OBSOLETE Input Impedance
GAIN CONTROL ELEMENTS
Default Step Size – Master
Default Step Size – Channel
Gain Error
Gain Match Error
Power On Mute Attenuation
AVMASTER = 0 dB to –60 dB
AVCHANNEL = 0 dB to +20 dB
Relative to Same Channel
AVMASTER = 0 dB
AVMASTER = –20 dB
AVMASTER = –40 dB
AVMASTER = –60 dB
Channel-to-Channel; Same Level Setting
AVMASTER = 0 dB
AVMASTER = –20 dB
AVMASTER = –20 dB, AVCH = +20 dB
AVMASTER = –40 dB
AVMASTER = –60 dB
VIN = +10 dBu
10
kΩ
1.0
dB
1.0
dB
0.25
dB
0.25
dB
1
dB
2
dB
0.25
dB
0.25
dB
0.25
dB
1
dB
2
dB
–100
dB
ANALOG OUTPUT
Output Impedance
5
Ω
Mute Output Impedance
5
Ω
Output Current
±2
mA
Minimum Resistive Load Drive
1
kΩ
Maximum Capacitive Drive
TBD
pF
Offset Voltage
Channel Muted
10
mV
CONTROL SECTION
Logic Input LO
Logic Input HI
Logic Input Current
Clock Frequency
Timing Characteristics
Logic LO or HI
See Timing Diagram
2.0
1
1
0.8
V
V
µA
2000
kHz
ANALOG COMMON OUTPUT
Output Voltage
Output Impedance
See Note 1
–5
+5
%
5.0
Ω
POWER SUPPLIES
Supply Voltage Range
Supply Current
Power Supply Rejection Ratio
Dual Supply
Single Supply
Positive
Negative
Dual Supply
±4
± 15
V
+8
+15
V
17
28
mA
17
28
mA
TBD
dB
NOTES
1Analog Common Output is used in single supply applications. It is nominally half the voltage between V+ and V–, e.g.,
V + – (V– ) .
2
Specifications subject to change without notice.
–2–
REV. A
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