MCP3905LT Просмотр технического описания (PDF) - Microchip Technology

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MCP3905LT

Energy-Metering ICs with Active (Real) Power Pulse Output

Microchip Technology 

MCP3905/06

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP3905/06

SSOP-24

Symbol

Definition

1

DVDD

Digital Power Supply Pin

2

HPF

High-Pass Filters Control Logic Pin

3

AVDD

Analog Power Supply Pin

4

NC

No Connect

5

CH0+

Non-Inverting Analog Input Pin for Channel 0 (Current Channel)

6

CH0-

Inverting Analog Input Pin for Channel 0 (Current Channel)

7

CH1-

Inverting Analog Input Pin for Channel 1 (Voltage Channel)

8

CH1+

Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)

9

MCLR

Master Clear Logic Input Pin

10

REFIN/OUT Voltage Reference Input/Output Pin

11

AGND

Analog Ground Pin, Return Path for internal analog circuitry

12

F2

Frequency Control for HFOUT Logic Input Pin

13

F1

Frequency Control for FOUT0/1 Logic Input Pin

14

F0

Frequency Control for FOUT0/1 Logic Input Pin

15

G1

Gain Control Logic Input Pin

16

G0

Gain Control Logic Input Pin

17

OSC1

Oscillator Crystal Connection Pin or Clock Input Pin

18

OSC2

Oscillator Crystal Connection Pin or Clock Output Pin

19

NC

No Connect

20

NEG

Negative Power Logic Output Pin

21

DGND

Digital Ground Pin, Return Path for Internal Digital Circuitry

22

HFOUT

High-Frequency Logic Output Pin (Intended for Calibration)

23

FOUT1

Differential Mechanical Counter Logic Output Pin

24

FOUT0

Differential Mechanical Counter Logic Output Pin

3.1 Digital VDD (DVDD)

DVDD is the power supply pin for the digital circuitry

within the MCP3905/06.

DVDD requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Please refer to Section 5.0 “Applications

Information”.

3.3 Analog VDD (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP3905/06.

AVDD requires appropriate bypass capacitors and

should be maintained to 5V ±10% for specified

operation. Please refer to Section 5.0 “Applications

Information”.

3.2 High-Pass Filter Input Logic Pin

(HPF)

HPF controls the state of the high-pass filter in both

input channels. A logic ‘1’ enables both filters,

removing any DC offset coming from the system or the

device. A logic ‘0’ disables both filters, allowing DC

voltages to be measured.

© 2009 Microchip Technology Inc.

DS21948E-page 11

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