UPD78C11AGF(A)-XXX-3BE Просмотр технического описания (PDF) - NEC => Renesas Technology

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UPD78C11AGF(A)-XXX-3BE

8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)

NEC => Renesas Technology 

µPD78C10A(A), 78C11A(A), 78C12A(A)

Table 3-1. Hardware States after Reset

Hardware

State after reset

During power-on reset

Previous contents are

retained

Internal data memory

RESET input During CPU

Write address data

during nor- write operation Other address data

mal operation Operation other than CPU write

RESET input during standby mode

Undefined

Previous contents are

retained

Expansion accumulators (EA, EA’)

Accumulators (A, A’)

General-purpose registers (B, C, D, E, H, L, B’, C’, D’, E’, H’, L’)

Working register’s vector registers (V, V’)

Undefined

5

Program counter (PC)

0000H

Stack pointer (SP)

Undefined

Mode registers (MA, MB, MC, MF)

FFH

Ports

MCC register

00H

MM register (bits MM0 to MM2)

0

Output latch for each port

Undefined

INTERRUPT ENABLE F/F

0

Interrupt

Request flag

0

Mask register

FFH

Test flags (except SB flag)

0

During power-on reset

1

During standby mode

Previous contents are

Standby flag (SB)

RESET input during normal operation

retained

Contents prior to RE- 5

SET input are retained

Timer mode register (TMM)

FFH

Timer

Timer F/F

0

Timer registers (TM0, TM1)

Undefined

Timer/event counter mode register (ETMM)

00H

Timer/event counter output mode register (EOM)

Timer/event counter

Timer/event counter registers (ETM0, ETM1)

Timer/event counter capture register (ECPT)

Undefined

Timer/event counter (ECNT)

5

Serial mode high register (SMH)

00H

Serial interface

Serial mode low register (SML)

48H

A/D channel mode register (ANM)

00H

MM register (MM3, RAE bit)

Undefined

Zero-cross mode register (bits ZC1 and ZC2)

1

19

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