LTC1664 Просмотр технического описания (PDF) - Linear Technology

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LTC1664

Micropower Quad 10-Bit DAC

Linear Technology 

LTC1664

Operation

load can be successfully driven by inserting a 20Ω resis-

tor; a 2.2µF load needs only a 10Ω resistor. In either case,

larger values of resistance, capacitance or both may be

safely substituted for the values given.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output DAC, the output is limited

to voltages within the supply range.

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 3b.

Similarly, limiting can occur near full-scale when the REF

pin is tied to VCC. If VREF = VCC and the DAC full-scale

error (FSE) is positive, the output for the highest codes

limits at VCC as shown in Figure 3c. No full-scale limiting

can occur if VREF is less than VCC – FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

VREF = VCC

POSITIVE

FSE

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

VREF = VCC

INPUT CODE

(3c)

OUTPUT

VOLTAGE

0

512

1023

INPUT CODE

(3a)

0V

NEGATIVE

OFFSET

INPUT CODE

(3b)

1664 F03

Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative

Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When VREF = VCC

1664fa

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