BR24A01AFJ-WM Просмотр технического описания (PDF) - ROHM Semiconductor
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BR24A01AFJ-WM Datasheet PDF : 32 Pages
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BR24Axxx-WM (1K 2K 4K 8K 16K 32K 64K)
●Operating timing characteristics (Unless otherwise specified, Ta=-40℃ to +105℃, VCC=2.5V to 5.5V)
FAST-MODE
STANDARD-MODE
Parameter
Symbol
2.5V≦VCC≦5.5V
2.5V≦VCC≦5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency
fSCL
-
-
400
-
-
100 kHz
Data clock “HIGH“ time
tHIGH
0.6
-
-
4.0
-
-
μs
Data clock “LOW“ time
tLOW
1.2
-
-
4.7
-
-
μs
SDA, SCL rise time *1
tR
-
-
0.3
-
-
1.0 μs
SDA, SCL fall time *1
tF
-
-
0.3
-
-
0.3 μs
Start condition hold time
tHD:STA 0.6
-
-
4.0
-
-
μs
Start condition setup time
tSU:STA
0.6
-
-
4.7
-
-
μs
Input data hold time
tHD:DAT
0
-
-
0
-
-
ns
Input data setup time
tSU:DAT 100
-
-
250
-
-
ns
Output data delay time
tPD
0.1
-
0.9
0.2
-
3.5 μs
Output data hold time
tDH
0.1
-
-
0.2
-
-
μs
Stop condition setup time
tSU:STO 0.6
-
-
4.7
-
-
μs
Bus release time before transfer start
tBUF
1.2
-
-
4.7
-
-
μs
Internal write cycle time
tWR
-
-
5
-
-
5
ms
Noise removal valid period (SDA, SCL terminal) tI
-
-
0.1
-
-
0.1 μs
WP hold time
tHD:W P
0
-
-
0
-
-
ns
WP setup time
tSU:W P
0.1
-
-
0.1
-
-
μs
WP valid time
tHIGH:WP 1.0
-
-
1.0
-
-
μs
*1 Not 100% tested
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same operations, and mode is changed. They are distinguished by operating
speeds. 100kHz operation is called STANDARD-MODE, and 400kHz operation is called FAST-MODE. This operating
frequency is the maximum operating frequency, so 100kHz clock may be used in FAST-MODE. At VCC =2.5V to 5.5V,
400kHz, namely, operation is made in FASTMODE. (Operation is made also in STANDARD-MODE.)
●Sync Data Input / Output Timing
tR
tF tHIGH
SCL
SDA
((in入pu力t) )
SDA
(o(u出tp力ut))
tHD:STA
tBUF
tSU:DAT tLOW
tHD:DAT
tPD
tDH
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
SCL
SDA
D0 ACK
Write data
(n-th address)
ｔWR
Stop condition
Start condition
Figure 1-(c) Write cycle timing
Figure 1-(b) Start-stop bit timing
SCL
SDA
DATA(1)
D1 D0 ACK
WP
DATA(n)
ACK
ｔWR
スSトtッopプcコoンndデitィioシn ョン
tSU：WP
ｔHD：WP
Figure 1-(d) WP timing at write execution
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
WP
ACK
tWR
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
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TSZ22111・15・001
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TSZ02201-0R1R0G100140-1-2
29.Jan.2018 Rev.003
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