CXD1852Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXD1852Q

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CXD1852Q

3-11. DRAM Interface AC Characteristics

3-11-1. Write Cycle

XRAS

XCAS0 to 3

XMWE

MA0 to 9

MD0 to 15

tRP

tPC

tRCD

tCAS

tCP

tWCS

tASR

tRAH

tASC

tCAH

tDS

tDH

tRSH

tWCH

Item

RAS precharge time

RAS to CAS delay time

RAS hold time

Fast page mode cycle time

CAS pulse width

CAS precharge time

Write command setup time

Write command hold time

Row address setup time

Row address hold time

Column address setup time

Column address hold time

Write data setup time

Write data hold time

Symbol

tRP

tRCD

tRSH

tPC

tCAS

tCP

tWCS

tWCH

tASR

tRAH

tASC

tCAH

tDS

tDH

Min.

∗1 tv is the basic clock cycle for the DRAM interface circuit.

∗2 Same as the DRAM interface read cycle.

Typ.

2 × tv

2 × tv

tv

2 × tv

tv

tv

tv

2 × tv

tv

tv

tv

tv

tv

tv

Max.

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Unit Remarks

ns ∗2

ns ∗2

ns ∗2

ns ∗2

ns ∗2

ns ∗2

ns

ns

ns ∗2

ns ∗2

ns ∗2

ns ∗2

ns

ns

– 16 –

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