Q67100-H5148 查看數據表（PDF） - Infineon Technologies

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Q67100-H5148

ICs for Consumer Electronics Quarter PIP Processor

Infineon Technologies 

SDA 9189X

2.3 PIP Field Memory

The on-chip memory has a capacity of 329184 bits. It stores one decimated field of the

inset picture. In the multi-PIP display modes the memory is able to store one decimated

field of every partial picture (e.g. during tuner scanning).

2.3.1 Picture Sizes

The picture size depends on the horizontal and vertical decimation factors.

Horizontal Decimation

2:1

3:1

4:1

6:1

Pixels/Line

288

192

144

96

Vertical Decimation

2:1

3:1

4:1

6:1

Lines/Field

(625 lines standard)

126

84

63

42

Lines/Field

(525 lines standard)

102

68

51

34

2.3.2 Memory Writing

To get equal clock frequencies for luminance and chrominance signals a multiplexer at

the memory input generates a 3-bit data format for both chrominance components.

In field mode display only every second inset field is written into the memory, in frame

mode display the memory is written continuously. Data are written with the lower inset

clock frequency depending on the horizontal decimation factor (6.75 MHz, 4.5 MHz,

3.375 MHz, or 2.25 MHz).

Memory writing can be stopped by program (FREEZE), a freeze picture display results

(one field).

In single-PIP display modes frame mode display is possible having no scan conversion

and the same number of lines in inset and parent channel (625 lines or 525 lines both).

The result is a higher vertical and temporal resolution because of displaying every

incoming field. The standards are analyzed internally and an activated frame mode

display is switched to field mode display automatically when the described restrictions

are no longer valid.

Semiconductor Group

21

03.96

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