CD4532BMS 查看數據表（PDF） - Intersil
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CD4532BMS Datasheet PDF : 9 Pages
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CD4532BMS
Logic Diagram
D1
* 11
VDD
16
D2
Q0
* 12
9
D3
* 13
D4
*1
D5
*2
D6
*3
D7
*4
D0
* 10
EI
*5
VDD
Q1
7
Q2
6
GS
14
E0
15
VSS
8
*ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 1. CD4532BMS LOGIC DIAGRAM
TRUTH TABLE
INPUT
OUTPUT
E1
D7
D6
D5
D4
D3
D2
D1
D0
GS
Q2
Q1
Q0
E0
0
X
X
X
X
X
X
X
X
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
X
X
X
X
X
X
X
1
1
1
1
0
1
0
1
X
X
X
X
X
X
1
1
1
0
0
1
0
0
1
X
X
X
X
X
1
1
0
1
0
1
0
0
0
1
X
X
X
X
1
1
0
0
0
1
0
0
0
0
1
X
X
X
1
0
1
1
0
1
0
0
0
0
0
1
X
X
1
0
1
0
0
1
0
0
0
0
0
0
1
X
1
0
0
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
X = Don’t Care
Logic 1 ≡ High
Logic 0 ≡ Low
7-1232
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