MSM6542-01/02/03
i) In the interrupt mode (when the IT/PLS1 bit is 1)
(i-1) When DP is 0:
"1"
IRQ FLAG1 "0"
IRQ FLAG0 "0"
¡ Semiconductor
Interrupt timing
The IRQ FLAG1 bit is read
(i-2) When DP is 1:
"1"
IRQ FLAG1 "0"
122µs
"1"
IRQ FLAG0 "0"
122µs
Interrupt timing
The IRQ FLAG1 bit is read
Note:
When the IRQ FLAG1 bit is read within the 122
µs interval with the MASK1 bit set at 1, it is not
cleared. The IRQ FLAG1 bit is cleared after the
122 µs interval ends.
ii) In the periodic pulse output mode (when the IT/PLS1 bit is 0)
"1"
IRQ FLAG2 "0"
IRQ FLAG0 "0"
Output timing
Automatic restoration
0 is written in the IRQ FLAG1 bit
with DP set at 0
88