IDT79R3500 查看數據表（PDF） - Integrated Device Technology

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IDT79R3500

RISC CPU PROCESSOR RISCore™

Integrated Device Technology 

IDT79R3500 RISC CPU PROCESSOR RISCore

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DESCRIPTION:

The IDT79R3500 RISC Microprocessor consists of three

tightly-coupled processors integrated on a single chip. The

first processor is a full 32-bit CPU based on RISC (Reduced

Instruction Set Computer) principles to achieve a new stan-

dard of microprocessor performance. The second processor

is a system control coprocessor, called CP0, containing a

fully-associative 64-entry TLB (Translation Lookaside Buffer),

MMU (Memory Management Unit) and control registers, sup-

porting a 4GB virtual memory subsystem, and a Harvard

Architecture Cache Controller achieving a bandwidth of

320MBs/second using industry standard static RAMs. The

third processor is the Floating Point Accelerator which per-

forms arithmetic operations on values in floating-point repre-

sentations. This processor fully conforms to the requirements

of ANSI/IEEE Standard 754-1985, “IEEE Standard for Binary

Floating-Point Arithmetic.” In addition, the architecture fully

supports the standard’s recommendations.

The programmer model of this device will be the same as

the programmer model of a system which uses a discrete

IDT79R3000 with the IDT79R3010: 32 integer registers, 16

floating point registers; co-processor 0 registers; floating point

status and control register; RISC integer ALU; Integer Multiply

and Divide ALU; Floating Point Add/Subtract, Multiply, and

Divide ALUs. The device pipeline will be the same as for the

IDT79R3000, as will the co-processor 0 functionality. No new

instructions have been introduced. Pin compatibility extends

to AC and DC characteristics, software execution and initial-

ization mode vector selection.

This data sheet provides an overview of the features and

architecture of the IDT79R3500 CPU, Revision 3.0. A more

detailed description of the operation of the device is incorpo-

rated in the R3500 Family Hardware User Manual, and a more

detailed architectural overview is provided in the MIPS RISC

Architecture book, both available from IDT. Documentation

providing details of the software and development environ-

ments supporting this processor are also available from IDT.

IDT79R3500 CPU Registers

The IDT79R3500 CPU provides 32 general purpose 32-

bit registers, a 32-bit Program Counter, and two 32-bit regis-

ters that hold the results of integer multiply and divide opera-

tions. Only two of the 32 general registers have a special

purpose: register r0 is hardwired to the value “0”, which is a

useful constant, and register r31 is used as the link register in

jump-and-link instructions (return address for subroutine calls).

The CPU registers are shown in Figure 2. Note that there

is no Program Status Word (PSW) register shown in this

figure: the functions traditionally provided by a PSW register

are instead provided in the Status and Cause registers incor-

porated within the System Control Coprocessor (CP0).

FPA REGISTERS

The IDT79R3010A FPA provides 32 general purpose 32-

bit registers, a Control/Status register, and a Revision Identi-

fication register.

Floating-point coprocessor operations reference three types

of registers:

• Floating-Point Control Registers (FCR)

• Floating-Point General Registers (FGR)

• Floating-Point Registers (FPR)

General Purpose Registers

31

0

r0

r1

r2

Multiply/Divide Registers

31

0

HI

31

0

LO

Program Counter

r29

31

0

r30

PC

r31

2871 drw 02

Figure 2. IDT79R3500 CPU Registers

Floating-Point General Registers (FGR)

There are 32 Floating-Point General Registers (FGR) on

the FPA. They represent directly-addressable 32-bit regis-

ters, and can be accessed by Load, Store, or Move Operations.

Floating-Point Registers (FPR)

The 32 FGRs described in the preceding paragraph are

also used to form sixteen 64-bit Floating-Point Registers

(FPR). Pairs of general registers (FGRs), for example FGR0

and FGR1 (Figure 3) are physically combined to form a single

64-bit FPR. The FPRs hold a value in either single- or double-

precision floating-point format. Double-precision format FPRs

are formed from two adjacent FGRs.

Floating-Point Control Registers (FCR)

There are 2 Floating-Point Control Registers (FCR) on the

FPA. They can be accessed only by Move operations and

include the following:

• Control/Status register, used to control and monitor ex-

ceptions, operating modes, and rounding modes;

• Revision register, containing revision information about

the FPA.

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