IS61SP12832-5TQ(1999) 查看數據表（PDF） - Integrated Silicon Solution

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IS61SP12832-5TQ
(Rev.:1999)

128K x 32 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Silicon Solution 

IS61SP12832

READ/WRITE CYCLE TIMING

CLK

ADSP

ADSC

ADV

A15-A0

tKC

tKH

tKL

tSS

tSH

tSS

tSH

tAS

tAH

RD1

tAVS

RD2

tWS

tWH

GW

tWS

tWH

BWE

ADSP is blocked by CE inactive

ADSC initiate read

tAVH

Suspend Burst

RD3

ISSI ®

BW4-BW1

CE

CE2

CE2

OE

DATAOUT

DATAIN

tCES

tCEH

CE Masks ADSP

tCES

tCEH

tCES

tCEH

tOEQ

CE2 and CE2 only sampled with ADSP or ADSC

tOEHZ

High-Z

High-Z

tOELZ

tKQLZ

tKQ

tOEQX

1a

Single Read

2a

2b

2c

2d

Burst Read

Pipelined Read

Unselected with CE2

tKQX

3a

tKQHZ

Unselected

Integrated Silicon Solution, Inc. — 1-800-379-4774

9

ADVANCE INFORMATION SR038-0D

04/16/99

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