AM85C30-8PC 查看數據表（PDF） - Advanced Micro Devices

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AM85C30-8PC

Enhanced Serial Communications Controller

Advanced Micro Devices 

Write Register 10

Write Register 12

AMD

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

6-Bit/8-Bit Sync

TC0

Loop Mode

Abort/Flag on Underrun

Mark/Flag Idle

TC1

TC2

TC3

Go Active on Roll

TC4

0 0 NRZ

TC5

0 1 NRZI

TC6

1 0 FM1 (Transition = 1)

TC7

1 1 FM0 (Transition = 0)

CRC Preset ‘1’ or ‘0’

Write Register 13

Lower Byte of

Time Constant

Write Register 14

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

TC8

TC9

TC10

TC11

TC12

TC13

TC14

TC15

Upper Byte of

Time Constant

BR Generator Enable

BR Generator Source

DTR/Request Function

Auto Echo

Local Loopback

Write Register 15

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 Null Command

0 0 1 Enter Search Mode

0 1 0 Reset Missing Clock

0 1 1 Disable DPLL

1 0 0 Set Source = BR Generator

1 0 1 Set Source = RTxC

1 1 0 Set FM Mode

1 1 1 Set NRZI Mode

* Added Enhancement

SDLC/HDLC Enhancements Enable*

Zero Count IE

10 × 19 Bit FIFO Enable*

DCD IE

Sync/Hunt IE

CTS IE

Tx Underrun/EOM IE

Break/Abort IE

10216F-13

(concluded)

Figure 9. Write Register Bit Functions (continued)

Am85C30 Timing

The ESCC generates internal control signals from WR

and RD that are related to PCLK. Since PCLK has no

phase relationship with WR and RD, the circuitry gener-

ating these internal control signals must provide time for

metastable conditions to disappear. This gives rise to a

recovery time related to PCLK. The recovery time ap-

plies only between bus transactions involving the

ESCC. The recovery time required for proper operation

is specified from the falling edge of WR or RD in the first

transaction involving the ESCC, to the falling edge of

WR or RD in the second transaction involving the

ESCC. This time must be at least 3 1/2 PCLK regardless

of which register or channel is being accessed.

Read Cycle Timing

Figure 10 illustrates Read cycle timing. Addresses on

A/B and D/C and the status on INTACK must remain sta-

ble throughout the cycle. If CE falls after RD falls or if it

rises before RD rises, the effective RD is shortened.

Write Cycle Timing

Figure 11 illustrates Write cycle timing. Addresses on

A/B and D/C and the status on INTACK must remain

stable throughout the cycle. If CE falls after WR falls or if

it rises before WR rises, the effective WR is shortened.

Data must be valid before the rising edge of WR.

Am85C30

23

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