NT5DS32M4AT 查看數據表（PDF） - Nanya Technology

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NT5DS32M4AT

128Mb Double Data Rate SDRAM

Nanya Technology 

NT5DS32M4AT

NT5DS16M8AT

128Mb Double Data Rate SDRAM

Block Diagram (32Mb x 4)

CKEn

CK

CK

CSn

WE

CAS

RAS

Mode

Registers

12

12

A0-A11,

BA0, BA1

14

2

2

11 Column-Address

Counter/Latch

QFC

generator

DRVR

QFC

(Optional)

Bank1 Bank2 Bank3

Clk

DLL

4096

Bank0

Memory

Array

(4096 x 1024 x 8)

Sense Amplifiers

I/O Gating

DM Mask Logic

1024

(x8)

Column

Decoder

10

COLo

1

8

8

8

Data

4

4

4

DQS

1

Generator

COLo Input

Register

Write Mask 1

1

FIFO

&

21

1

Drivers

84

4

clk

out

cilnk

4

Data

4

DQS

1

4

Clk

COLo

1

DQ0-DQ3,

DM

DQS

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

REV 1.0

May, 2001

5

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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