PEF3065NV3.2 查看數據表（PDF） - Infineon Technologies
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PEF3065NV3.2 Datasheet PDF : 102 Pages
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PEB 3065
PEF 3065
Programming the SLICOFI®
5
Programming the SLICOFI®
With the appropriate commands, the SLICOFI can be programmed and verified very
flexible via the IOM-2 Interface monitor channel.
Data transfer to the SLICOFI starts with a SLICOFI-specific address byte (81H).
With the second byte one of 3 different types of commands (SOP, TOP or COP) is
selected. SOP and COP can be used as a write or read command, the TOP-Command
is used for reading only. Due to the extended SLICOFI feature control facilities, SOP,
COP and TOP commands contain additional information (e.g. number of subsequent
bytes) for programming (write) and verifying (read) the SLICOFI status.
A write command is followed by up to 8 bytes of data. The SLICOFI responds to a read
command with its IOM2 specific address and the requested information, that is up to 15
bytes of data (see chapter 5.2).
Attention: Each byte on the monitor channel has to be sent twice at least according to
the IOM2 Monitor handshake procedure. (For more information on IOM-2 specific
Monitor Channel Data Structure see chapter 10).
5.1
Types of Monitor Bytes
The 8-bit Monitor bytes have to be interpreted as either commands or status information
stored in Configuration Registers or the Coefficient Ram. There are three different types
of SLICOFI commands which are selected by bit 2 and 3 as shown below.
(x… don’t care)
SOP Status Operation:
SLICOFI status setting/monitoring
Bit
7
6
5
4
3
2
1
0
0
1
TOP
Bit
Transfer Operation:
7
6
5
Read Certain Status Options only
4
3
2
1
0
1
1
COP
Bit
Coefficient Operation:
7
6
5
filter coefficient setting/monitoring
4
3
2
1
0
x
0
Storage of programming information:
8 (9) status configuration registers:
(SCR0), SCR1, … SCR8 accessed by SOP
commands
Semiconductor Group
19
01.98
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