ST72652C4T1 查看數據表（PDF） - STMicroelectronics

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ST72652C4T1

LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI

STMicroelectronics 

ST7265x

COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

13.11.3 I2C - Inter IC Control Interface

Parameter

I2C-Bus Timings

Standard I2C

Min

Max

Fast I2C

Min

Max

Symbol Unit

Bus free time between a STOP and START con-

dition

4.7

1.3

TBUF

ms

Hold time START condition. After this period,

4.0

0.6

the first clock pulse is generated

THD:STA µs

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Data hold time

Data set-up time

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

4.7

4.0

4.7

0 (1)

250

1000

300

1.3

0.6

0.6

0 (1)

100

20+0.1Cb

20+0.1Cb

0.9(2)

300

300

TLOW

µs

THIGH

µs

TSU:STA µs

THD:DAT ns

TSU:DAT ns

TR

ns

TF

ns

Set-up time for STOP condition

Capacitive load for each bus line

4.0

0.6

400

TSU:STO ns

400

Cb

pF

1) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge

the undefined region of the falling edge of SCL

2) The maximum hold time of the START condition has only to be met if the interface does not stretch the

low period of SCL signal

Cb = total capacitance of one bus line in pF

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