TEA6360/V2 查看數據表（PDF） - Philips Electronics
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TEA6360/V2 Datasheet PDF : 15 Pages
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Philips Semiconductors
5-band stereo equalizer circuit
Preliminary specification
TEA6360
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VN
weighted output noise voltage
CCIR 468-3, maximum
(RMS value)
gain/filter of 12 dB
defeat mode
−
8
16
µV
all filters linear
−
23
46
µV
all filters maximum boost
−
70
140
µV
all filters maximum cut
−
23
46
µV
αCr
crosstalk between bus inputs and signal
outputs, 20 log (Vbus(p-p)/Vo rms)
all filters linear
−
120
−
dB
RR
ripple rejection at Vripple rms < 200 mV all filters linear
for f = 100 Hz
−
70
−
dB
for f = 40 to 12500 Hz
−
60
−
dB
Internal filters of analog part
Q
Rtot
∆Rtot
Q-factor dependent on maximum gain
maximum gain 10 dB
maximum gain 12 dB
maximum gain 15 dB
total resistor of different filter sections
tolerance between any filter section
0.1
−
1.2
0.1
−
1.4
0.1
−
1.8
29.6 37.0 44.4 kΩ
−
−
±4
%
Internal controls of analog part via I2C-bus
Step
∆Vo
number of steps for boost or for cut
position for linear
step resolution
step set error
DC offset between any step or
neighbouring step or defeat
−
−
maximum gain 12 dB −
−
−
5
−
1
−
2.4
−
dB
0.5
−
dB
−
±10
mV
I2C-bus control SDA and SCL (pins 15 and 16)
VIH
VlL
II
VACK
input level HIGH
input level LOW
input current
acknowledge voltage on SDA
3
−
VP
V
0
−
1.5
V
−
−
±10
µA
l15 = 3 mA at LOW
−
−
0.4
V
Module address bit (pin 18)
VIH
input level HIGH for address 1000 0110
VIL
input level LOW for address 1000 0100
II
input current
3
−
Vp
V
0
−
1.5
V
−
−
±10
µA
Power on reset: When reset is active the DEF-bit (defeat) is set and the I2C-bus receiver is in reset position.
RESET start of reset
end of reset
increasing VP
decreasing VP
increasing VP
−
−
2.5
V
4.2
5.0
5.8
V
5.2
6.0
6.8
V
May 1991
7
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