NC7SZ74 查看數據表（PDF） - Fairchild Semiconductor
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NC7SZ74 Datasheet PDF : 9 Pages
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Connection Diagrams
IEEE/IEC
Pin Configurations
Figure 1. Logic Symbol
Figure 2. US8 (Top View)
Pin Definitions
Pin # US8
1
2
3
4
5
6
7
8
Pin # MicroPak
7
6
5
4
3
2
1
8
Function Table
Inputs
/CLR
/PR
D
CK
L
H
H
L
L
L
H
H
H
H
H
H
H = HIGH Logic Level
L = LOW Logic Level
X
X
X
X
X
X
L
H
X
Qn = No change in data
Z = High Impedance
Figure 3. MicroPak™ (Top Through View)
Name
CK
D
/Q
GND
Q
/CLR
/PR
VCC
Description
Clock Pulse Input
Data Input
Flip-Flop Output
Ground
Flip-Flop Output
Direct Clear Input
Direct Preset Input
Supply Voltage
Output
Q
/Q
L
H
H
L
H
Qn
X = Immaterial
= Rising Edge
H
L
H
H
L
/Qn
Falling Edge
Function
Clear
Preset
No Change
© 2001 Fairchild Semiconductor Corporation
NC7SZ74 • Rev. 1.0.2
2
www.fairchildsemi.com
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