GT-6816 查看數據表（PDF） - Unspecified

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GT-6816

SCANNER Chips

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GT-6816

Referenced period for 6-bits dot clock counter:

CPU Read/Write

Address: FF01H

Bit Reset Description

7:6 2’b0 Reserved

Defines the referenced period (N+1) cycles of the 6 bits dot clock counter.

5:0 6’b0 The 6-bits dot clock counter is referenced by master clock (48MHz). Dot

clock is defined by this N+1 cycles referenced to 6-bits dot clock counter.

Referenced period for 6-bits pixel clock counter:

CPU Read/Write

Address: FF02H

Bit Reset Description

7:6 2’b0 Reserved

Defines the referenced period (N+1) cycles of the 6 bits pixel clock

counter. The 6-bits pixel clock counter is referenced by master clock

(48MHz). Pixel clock is defined by this N+1 cycles referenced to 6-bits

5:0 6’b0

pixel clock counter.

The programmable timing control signal for sensor and AFE are

referenced to pixel clock.

Referenced period high byte for 16-bits counter of timing generator:

CPU Read/Write

Address: FF03H

Bit Reset Description

7:0 8’b0 Period for 16-bits counter high byte

Referenced period low byte for 16-bits counter of timing generator:

Address: FF04H

Bit Reset Description

Period for 16-bits counter low byte.

These two registers define the period (N+1) cycles of 16-bits counter

7:0 8’b0

referenced to pixel clock. All programmable timing control signals are

referenced to this 16-bits counter.

AFE ADCLK rising phase control

CPU Read/Write

Address: FF05H

Bit Reset Description

7:6 2’b0 Reserved

5:0 6’b0 Define ADCLK rising phase referenced to 6-bits dot clock counter

AFE ADCLK falling phase control

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