GT-6816
CPU Read/Write
Address: FF06H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define ADCLK falling phase referenced to 6-bits dot clock counter
Sensor TG control signal rising phase referenced to pixel counter
CPU Read/Write
Address: FF07H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define TG rising phase reference to 6-bits pixel counter
Sensor TG control signal falling phase referenced to pixel counter
Address: FF08H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define TG falling phase referenced to 6-bits pixel counter
Sensor TG signal rising phase referenced to 16-bits counter:
CPU Read/Write
Address: FF09H
Bit Reset Description
7:0 8’b0 Define TG rising phase referenced to 16-bit counter
Sensor TG signal falling phase referenced to 16-bits counter:
CPU Read/Write
Address: FF0AH
Bit Reset Description
7:0 8’b0 Define TG falling phase referenced to 16-bit counter
Note :
The conditions for rising and falling only available during first 256 cycles of 16-bits
counter. For cycle exceeds 256 of 16-bits counter, TG output ‘0’ state.
Sensor TG control signal configuration
CPU Read/Write
Address: FF0BH
Bit Reset Description
7:6 8’b0 Reserved
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