GT-6816
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor SHS control signal rising phase
CPU Read/Write
Address: FF18H
Bit Reset Description
SHS polarity
7
1’b0 0 = normal operation
1 = invert SHS output
SHS enable
6
1’b0 0 = disable SHS ouptut
1 = enable SHS output
5:0 6’b0 Define rising phase referenced to 6-bits pixel clock counter
Sensor SHS control signal falling phase
CPU Read/Write
Address: FF19H
Bit Reset Description
7:6 2’b0 Reserved
5:0 6’b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor H1 control signal rising phase
CPU Read/Write
Address: FF1AH
Bit Reset Description
H1 polarity
7
1’b0 0 = normal operation.
1 = invert H1 output
H1 enable
6
1’b0 0 = disable H1 output
1 = enable H1 output
5:0 6’b0 Define rising phase referenced to 6-bits pixel clock counter
Sensor H1 control signal falling phase
CPU Read/Write
Address: FF1BH
Bit Reset Description
7
1’b0 H1 half enable
H1 masking function enable
6
1’b0 0 = disable masking function
1 = enable masking function
17