GT-6816 查看數據表（PDF） - Unspecified

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GT-6816

SCANNER Chips

Unspecified 

GT-6816

5:0 6’b0 Define rising phase referenced to 6-bits pixel counter

AFE CCLP1 control signal falling phase

CPU Read/Write

Address: FF25H

Bit Reset Description

7:6 2’b0 Reserved

5:0 6’b0 Define falling phase referenced to 6-bits pixel counter

AFE CLAMP2 control signal rising phase

CPU Read/Write

Address: FF26H

Bit Reset Description

7:0 8’b0 Define rising phase referenced to 16-bits counter

AFE CLAMP2 control signal falling phase

CPU Read/Write

Address: FF27H

Bit Reset Description

7:0 8’b0 Define falling phase referenced to 16-bits counter

Note:

These two registers define the rising and falling phase of CLAMP2 control signal, and

only available on the first 256 cycles of 16-bits counter. CLAMP2 output ‘0’ when

16-bits counter exceeds 256 cycle.

AFE CCLP2 control signal rising phase

CPU Read/Write

Address: FF28H

Bit Reset Description

CLAMP2 enable

7

1’b0 0 = CLAMP2 output disable

1 = CLAMP2 output enable

CCLP2 enable

6

1’b0 0 = CCLP2 output disable

1 = CCLP2 output enable

5:0 6’b0 Define rising phase referenced to 6-bits pixel counter

AFE CCLP2 control signal falling phase

CPU Read/Write

20

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