MCP23008/MCP23S08
1.6.4
DEFAULT COMPARE (DEFVAL)
REGISTER FOR INTERRUPT-ON-
CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
interrupt to occur.
REGISTER 1-4:
DEFVAL – DEFAULT VALUE REGISTER (ADDR 0x03)
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
DEF7
DEF6
DEF5
DEF4
DEF3
DEF2
bit 7
R/W-0
DEF1
R/W-0
DEF0
bit 0
bit 7-0
DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from
defaults <7:0>. Refer to INTCON.
If the associated pin level is the opposite from the register bit, an interrupt occurs.
Refer to INTCON and GPINTEN.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc.
DS21919B-page 11