MCP23008/MCP23S08
1.6.8
INTERRUPT FLAG (INTF)
REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt.
This register is ‘read-only’. Writes to this register will be
ignored.
Note:
INTF will always reflect the pin(s) that
have an interrupt condition. For example,
one pin causes an interrupt to occur and is
captured in INTCAP and INF. If, before
clearing the interrupt, another pin changes
which would normally cause an interrupt, it
will be reflected in INTF, but not INTCAP.
REGISTER 1-8:
INTF – INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0
R-0
R-0
R-0
R-0
INT7
INT6
INT5
INT4
INT3
bit 7
R-0
INT2
R-0
INT1
R-0
INT0
bit 0
bit 7-0
INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if
interrupts are enabled (GPINTEN) <7:0>.
1 = Pin caused interrupt.
0 = Interrupt not pending.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc.
DS21919B-page 15