AD7714YRUZ 查看數據表（PDF） - Analog Devices
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AD7714YRUZ Datasheet PDF : 40 Pages
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AD7714
TIMING CHARACTERISTICS1, 2
(AVDD = DVDD = +2.7 V to +5.25 V; AGND = DGND =
Logic 1 = DVDD unless otherwise noted.)
0 V; fCLKIN = 2.5␣ MHz; Input Logic 0 = 0 V,
Parameter
Limit at TMIN, TMAX
(A, Y Versions)
Units
Conditions/Comments
fCLKIN3, 4
tCLK IN LO
tCLK IN HI
tDRDY
t1
t2
Read Operation
t3
t4
t56
t6
t7
t8
t97
t10
Write Operation
t11
t12
t13
t14
t15
t16
400
2.5
0.4 × tCLK IN
0.4 × tCLK IN
500 × tCLK IN
100
100
0
0
0
80
100
100
100
0
10
60
100
100
0
30
20
100
100
0
kHz min
Master Clock Frequency: Crystal/Resonator or Externally
Supplied
MHz max
ns min
For Specified Performance
Master Clock Input Low Time. tCLK IN = 1/fCLK IN
2
ns min
Master Clock Input High Time
ns nom
DRDY High Time
ns min
SYNC Pulsewidth
ns min
RESET Pulsewidth
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
DRDY to CS Setup Time
CS Falling Edge to SCLK Active Edge Setup Time5
SCLK Active Edge to Data Valid Delay5
DVDD = +5␣ V
DVDD = +3␣ V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Active Edge Hold Time5
Bus Relinquish Time after SCLK Active Edge5
DVDD = +5␣ V
DVDD = +3␣ V
SCLK Active Edge to DRDY High5, 8
ns min
ns min
ns min
ns min
ns min
ns min
CS Falling Edge to SCLK Active Edge Setup Time5
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge to SCLK Edge Hold Time
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV DD) and timed from a voltage level of 1.6 V.
2See Figures 6 and 7. Timing applies for all grades.
3CLKIN Duty Cycle range is 45% to 55%. CLKIN must be supplied whenever the AD7714 is not in standby mode. If no clock is present in this case, the device can
draw higher current than specified and possibly become uncalibrated.
4The AD7714 is production tested with fCLKIN at 2.4576␣ MHz (1␣ MHz for some IDD tests). It is guaranteed by characterization to operate at 400␣ kHz.
5SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.
6These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V OL or VOH limits.
7These numbers are derived from the measured time taken by the data output to change 0.5␣ V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
8DRDY returns high after the first read from the device after an output update. The same data can be read again, if required, while DRDY is high although care
should be taken that subsequent reads do not occur close to the next output update.
Specifications subject to change without notice.
ORDERING GUIDE
ISINK (800A AT DVDD = +5V
100A AT DVDD = +3.3V)
TO OUTPUT
PIN
50pF
+1.6V
ISOURCE (200A AT DVDD = +5V
100A AT DVDD = +3.3V)
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
REV. C
Model
AVDD Temperature
Supply Range
Package
Option*
AD7714AN-5
5V
AD7714AR-5
5V
AD7714ARS-5
5V
AD7714AN-3
3V
AD7714AR-3
3V
AD7714ARS-3
3V
AD7714YN
3 V/5 V
AD7714YR
3 V/5 V
AD7714YRU
3 V/5 V
AD7714AChips-5 5 V
AD7714AChips-3 3 V
EVAL-AD7714-5EB 5 V
EVAL-AD7714-3EB 3 V
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +85°C
–40°C to +85°C
Evaluation Board
Evaluation Board
N-24
R-24
RS-28
N-24
R-24
RS-28
N-24
R-24
RU-24
Die
Die
*N = Plastic DIP; R = SOIC; RS = SSOP; RU = Thin Shrink Small Outline.
–7–
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