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5.3 Suggested Serial Command Settings
Power ON
VDD, VDDIO
INPUT
DATA
Register :
R0
>100us
DEN / VSYNC / HSYNC / DCLK / DATA INPUT
0020h
DCLK polarity control.
5.4 3-wire Registers Function Description
R0: Timing Controller Function Register
Designation
DITHB
NFSEL
FPOL
CLKPOL
VSDPOL
HSDPOL
Address
R0[0]
R0[3]
R0[4]
R0[5]
R0[6]
R0[7]
Description
Dithering control bit.
DITHB=”1”, Dithering off, (7-bits resolution, truncation last 1-bits of the input
data) DITHB=”0”, Dithering on, (Pseudo 8-bits resolution). (Default)
Narrow display mode selection bit.
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NFSEL=”1”: Narrow display format is enable.
NFSEL=”0”: Normally display. (Default)
VCOM polarity inverse control bit.
When FPOL=”1”, VCOM inverse polarity.
When FPOL=”0”, VCOM normal polarity. (Default)
DCLK polarity control bit.
CLKPOL=”1”: Data sampling at DCLK falling edge.
CLKPOL=”0”: Data sampling at DCLK rising edge. (Default)
VSD polarity control bit.
VSDPOL=”1”: VSD positive polarity.
VSDPOL=”0”: VSD negative polarity. (Default)
HSD polarity control bit.
VSDPOL=”1”: HSD positive polarity.
VSDPOL=”0”: HSD negative polarity. (Default)
Narrow display mode
1440 dots
180 dots
1080 dots
180 dots
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