QS5LV919 查看數據表（PDF） - Integrated Device Technology
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QS5LV919 Datasheet PDF : 12 Pages
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QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
INDUSTRIAL TEMPERATURE RANGE
GND 1
Q5
2
VDD
3
OE/RST 4
FEEDBACK 5
REF_SEL 6
SYNC0
7
AVDD
8
PE 9
AGND 10
SYNC1
11
FREQ_SEL 12
GND 13
Q0
14
28
Q4
27
VDD
26
2xQ
25
Q/2
24
GND
23
Q3
22
VDD
21
Q2
20
GND
19
LOCK
18
PLL_EN
17
GND
16
Q1
15
VDD
4 3 2 1 28 27 26
FEEDBACK 5
25 Q/2
REF_SEL 6
24 GND
SYNC0 7
23 Q3
AVDD 8
22 VDD
PE 9
21 Q2
AGND 10
20 GND
SYNC1 11
19 LOCK
12 13 14 15 16 17 18
QSOP
TOP VIEW
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating
Max.
Unit
VDD, AVDD Supply Voltage to Ground
–0.5 to +7
V
DC Input Voltage VIN
–0.5 to +5.5
V
Maximum Power
QSOP
655
mW
Dissipation (TA = 85°C) PLCC
770
mW
TSTG StorageTemperatureRange
–65 to +150
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = 25°C, f = 1MHz, VIN = 0V)
QSOP
PLCC
Parameter Typ.
Max.
Typ.
Max.
Unit
CIN
3
4
4
6
pF
2
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