SSD1809 查看數據表（PDF） - Solomon Systech

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SSD1809

LCD Segment / Common Driver With Controller

Solomon Systech  

Bit Pattern

01101011

011011X 1X 0

0111000X 0

0111001X 0

0111010X 0

0111011X 0

01111000

01111001

0111101X 0

0111110X 0

0111111X 0

1X6X5X4X 3X2X1X0

Command

Set Frame Frequency

Set Temperature Coefficient

Increase/Decrease Contrast Value

Reserved

Set DC-DC Converter Mode

Reserved

Reserved

Reserved

Set External / Internal Oscillator

Reserved

Set Oscillator Enable

Set GDDRAM Column Address

Comment

Next command (byte) on D3~D0 will be written to the Frame Fre-

quency Register.

D3D2D1D0 = 0000 : Frame Frequency Register = 0

D3D2D1D0 = 0001 : Frame Frequency Register = 1

D3D2D1D0 = 0010 : Frame Frequency Register = 2

:

:

:

D3D2D1D0 = 0101 : Frame Frequency Register = 5 (POR)

:

:

:

D3D2D1D0 = 1111 : Frame Frequency Register = 15

*D7~D4 : Don’t care.

X1X0=00: 0.00% (POR)

X1X0=11: -0.35%

X0=0: Decrease by one level

X0=1: Increase by one level

X0=0 : Normal Mode (POR)

X0=1 : Regulated Mode

X0=0: Internal Oscillator (POR)

X0=1: External Oscillator

For internal oscillator mode, place a resistor between OSC1 and

OSC2 pins. For external oscillator mode, feed clock input to OSC2

pin.

X0=0: Oscillator Master Disable(POR)

X0=1: Oscillator Master Enable

This is the master control for oscillator circuitry. This command

should be issued after the “External/Internal Oscillator” command.

Set GDDRAM Column Address.Use X6X5X4X3X2X1X0 as address

bits. MSB of the address set by “Set MSB of GDDRAM column

address command.

SSD1809

20

REV1.3

03/02

SOLOMON

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