Table 16 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V)
Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
PW CSL
PW CSH
tR
tF
Parameter
Clock Cycle Time (write cycle)
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
Read Data Hold Time
Output Disable Time
Access Time (RAM)
Access Time (command)
Chip Select Low Pulse Width (read RAM)
Chip Select Low Pulse Width (read Command)
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
Chip Select High Pulse Width (write)
Rise Time
Fall Time
Min Typ
100 500
0
-
0
-
30
-
5
-
10
-
-
-
15
-
15
-
250
-
250
-
50
-
100
-
50
-
-
-
-
-
Max Unit
-
ns
25
ns
-
ns
-
ns
-
ns
50
ns
40
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
10
ns
10
ns
R/W
D/C
E
CS
D0 -D7
(Write data to driv er)
(Read daDta0-fDro7m driv er)
tAS
tAH
PW CSL
t cycle
PW CSH
tF
tR
tDSW
tDHW
Valid Data
tACC
Valid Data
t DHR
tOH
Figure 15 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)
39
SSD1858
Rev 1.1
09/2002
SOLOMON