SSD1818Z(Rev1_2) 查看數據表（PDF） - Solomon Systech

零件编号

产品描述 (功能)

生产厂家

SSD1818Z
(Rev.:Rev1_2)

LCD Segment / Common Driver with Controller

Solomon Systech  

FUNCTIONAL BLOCK DESCRIPTIONS

Command Decoder and Command Interface

This module determines whether the input signal is interpreted as data or command. Input is directed to

this module based on the input of the D/ C pin.

If the D/ C pin is high, input is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at

D7-D0 is interpreted as a Command. It will be decoded and written to the corresponding command register.

MPU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D7-D0), R/ W ( WR ), D/ C , E/( RD ), CS1 and

CS2.

Read cycle

R/ W ( WR ) input high indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the

status register. In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline

processing is internally performed which requires the insertion of a dummy read before the first actual

display data read. This is shown in Figure 3.

R/W(WR )

E(RD)

data bus

N

n

n+1

n+2

write column address

dummy read

data read1

data read 2

data read 3

Figure 3 - Display Data Read Back Procedure - Insertion of Dummy Read

Write cycle

R/ W ( WR ) input Low indicates a write operation to Display Data RAM or Internal Command Registers

depending on the D/ C input. The E( RD ) input serves as data latch signal (clock) when high, provided that

the CS1 is pulled low and the CS2 is pulled high respectively.

Please refer to Figure 9 on Page 34 for Parallel Interface Timing Diagram of 6800-series microprocessors.

MPU Parallel 8080-series interface

The parallel interface consists of 8 bi-directional data pins (D7-D0), E/( RD ), R/ W ( WR ), D/ C , CS1 and

CS2.

SSD1818 Series

Rev 1.2

08/2002

12

SOLOMON

Share Link: