MC74AC109M 查看數據表（PDF） - ON Semiconductor

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MC74AC109M

Dual JK Positive Edge−Triggered Flip−Flop

ON Semiconductor 

MC74AC109, MC74ACT109

AC OPERATING REQUIREMENTS (continued)

Symbol

Parameter

trec

Recovery TIme

CDn or SDn to CP

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

CAPACITANCE

Symbol

Parameter

CIN

Input Capacitance

CPD

Power Dissipation Capacitance

74ACT

74ACT

VCC*

(V)

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Unit

Fig.

No.

Typ

Guaranteed Minimum

5.0

−

0

0

ns

3−9

Value

Typ

Unit

4.5

pF

35

pF

Test Conditions

VCC = 5.0 V

VCC = 5.0 V

DIP−16

MC74AC109N

AWLYYWW

MC74ACT109N

AWLYYWW

MARKING DIAGRAMS

SO−16

TSSOP−16

AC109

AWLYWW

AC

109

ALYW

ACT109

AWLYWW

ACT

109

ALYW

A

= Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

EIAJ−16

74AC109

ALYW

74ACT109

ALYW

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