CY2291 查看數據表（PDF） - Cypress Semiconductor
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CY2291 Datasheet PDF : 14 Pages
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CY2291
Switching Characteristics, Industrial 5.0V
Parameter
Name
t1
Output Period
Description
Clock output range,
5V operation
CY2291I
CY2291FI
Output Duty
Cycle[11]
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT > 66 MHZ
Duty cycle for outputs, defined as t2 ÷ t1[12]
fOUT < 66 MHZ
t3
Rise Time
Output clock rise time[13]
t4
Fall Time
Output clock fall time[13]
t5
Output Disable Time for output to enter three-state mode after
Time
SHUTDOWN/OE goes LOW
t6
Output Enable Time for output to leave three-state mode after
Time
SHUTDOWN/OE goes HIGH
t7
Skew
Skew delay between any identical or related
outputs[3, 12, 15]
t8
CPUCLK Slew Frequency transition rate
t9A
Clock Jitter[14] Peak-to-peak period jitter (t9A Max. – t9A
min.),% of clock period (fOUT < 4 MHz)
t9B
Clock Jitter[14] Peak-to-peak period jitter (t9B Max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
t9C
Clock Jitter[14] Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
t9D
Clock Jitter[14] Peak-to-peak period jitter
(fOUT > 50 MHz)
t10A
Lock Time for Lock Time from Power-Up
CPLL
t10B
Lock Time for Lock Time from Power-Up
UPLL and SPLL
Slew Limits
CPU PLL Slew Limits CY2291I
CY2291FI
Min.
11.1
(90 MHz)
12.5
(80 MHz)
40%
Typ.
50%
Max.
Unit
13000
ns
(76.923 kHz)
13000
ns
(76.923 kHz)
60%
45%
50%
55%
3
5
ns
2.5
4
ns
10
15
ns
10
15
ns
< 0.25
0.5
ns
1.0
<0.5
20.0
MHz/
ms
1
%
<0.7
1
ns
<400
500
ps
<250
350
ps
<25
50
ms
<0.25
1
ms
8
90
MHz
8
80
MHz
Document #: 38-07189 Rev. *A
Page 9 of 14
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