IDT72V36110L6BBGI 查看數據表（PDF） - Integrated Device Technology

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IDT72V36110L6BBGI

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

Integrated Device Technology 

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

65,536 x 36 and 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

REN

Q0 - Qn

Wx

tENH

tRTS

tA

WCLK

WEN

RT

EF

PAE

HF

tRTS

tENS

1

Wx+1

tSKEW2

1

2

2

tENS

tA

W1 (3)

tENH

tA

W2 (3)

tENH

tREF

tHF

tREF

tPAES

PAF

tPAFS

6117 drw16

NOTES:

1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.

2. OE = LOW.

3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.

4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.

D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.

5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.

6. RM is set HIGH during MRS.

Figure 11. Retransmit Timing (IDT Standard Mode)

31

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