MAX9526ATJ/V(2010) 查看數據表（PDF） - Maxim Integrated

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MAX9526ATJ/V
(Rev.:2010)

Low-Power, High-Performance NTSC/PAL Video Decoder

Maxim Integrated 

Low-Power, High-Performance

NTSC/PAL Video Decoder

LLC

D9–D2

HS

VS = 1

VS = 0

2 CLK 1 CLK

2 CLK

Figure 17. Horizontal and Vertical Sync Timing

PLL Control Register

REG

B7

B6

B5

B4

B3

B2

B1

B0

0x0E

0

0

LLC_MODE

PLLBYP

PLLBW

Line-Locked Clock Mode (LLC_MODE)

0X = Async mode or line-locked mode is set automati-

cally (default).

10 = PLL is forced to line-locked mode.

11 = PLL is forced to async mode.

PLL Bypass Mode (PLLBYP)

When PLLBYP = 1, the ADC and the decoder use the

input crystal or clock (XTAL/OSC, XTAL2) directly.

1 = Bypass the PLL.

0 = PLL is enabled (default).

Miscellaneous Register

Line-Locked PLL Tracking Speed (PLLBW)

PLLBW controls a digital loop filter that sets the band-

width of the line-locked PLL.

000 = 180Hz

001 = 250Hz

010 = 375Hz

011 = 500Hz (default)

100 = 750Hz

101 = 1kHz

110 = 1.5kHz

111 = 2kHz

REG

B7

B6

B5

B4

B3

B2

B1

B0

0x0F

0

0

DISAAFLT

1

SSLICE

Disable Digital Anti-Aliasing Filter (DISAAFLT)

Disable the digital anti-aliasing filter following the ADC.

1 = Disables filter.

0 = Enables filter (default).

Sync Slicing Level (SSLICE)

Sets the sync slicing level.

1111 = Slice at 240 (decimal), near the blanking level.

1000 = Slice at 128 (decimal), near the center of the

sync (default).

0100 = Slice at 64 (decimal), about 25% of the sync.

0000 = Slice at 0 (decimal), near the bottom of the

sync.

All values between 0000 and 1111 are valid.

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