74LVC16374ADGG 查看數據表（PDF） - Philips Electronics

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74LVC16374ADGG

16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State)

Philips Electronics 

Philips Semiconductors

16-bit edge triggered D-type flip-flop with 5 Volt

tolerant inputs/outputs (3-State)

Product specification

74LVC16374A/

74LVCH16374A

FEATURES

• 5 volt tolerant inputs/outputs for interfacing with 5V logic

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple power and ground pins for minimum

noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold (74LVCH16374A only)

• High impedance when VCC = 0

PIN CONFIGURATION

1OE 1

1Q0 2

1Q1 3

GND 4

1Q2 5

1Q3 6

VCC 7

1Q4 8

1Q5 9

GND 10

48 1CP

47 1D0

46 1D1

45 GND

44 1D2

43 1D3

42 VCC

41 1D4

40 1D5

39 GND

1Q6 11

38 1D6

DESCRIPTION

The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring

separate D-type inputs for each flip-flop and 3-State outputs for bus

oriented applications. The 74LVC16374A consists of 2 sections of

eight positive edge-triggered flip-flops. A clock (CP) input and an

output enable (OE) are provided for each octal. Inputs can be driven

from either 3.3V or 5V devices. In 3-State operation, outputs can

handle 5V. These features allow the use of these devices in a mixed

3.3V/5V environment.

The flip-flops will store the state of their individual D-inputs that meet

the set-up and hold time requirements on the LOW-to-HIGH CP

transition.

When OE is LOW, the contents of the flip-flops are available at the

outputs. When OE is HIGH, the outputs go to the high impedance

OFF-state. Operation of the OE input does not affect the state of the

flip-flops.

The 74LVCH16374A bus hold data inputs eliminates the need for

external pull up resistors to hold unused inputs.

1Q7 12

2Q0 13

2Q1 14

GND 15

2Q2 16

2Q3 17

VCC 18

2Q4 19

2Q5 20

GND 21

2Q6 22

2Q7 23

2OE 24

37 1D7

36 2D0

35 2D1

34 GND

33 2D2

32 2D3

31 VCC

30 2D4

29 2D5

28 GND

27 2D6

26 2D7

25 2CP

SW00074

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

Cp to Qn

CL = 50pF

VCC = 3.3V

fMAX

Maximum clock frequency

CI

Input capacitance

CPD

Power dissipation capacitance per flip-flop VCC = 3.3V1

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL × VCC2 × fo) = sum of outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

48-Pin Plastic SSOP Type III

–40°C to +85°C

74LVC16374A DL

48-Pin Plastic TSSOP Type II

–40°C to +85°C

74LVC16374A DGG

48-Pin Plastic SSOP Type III

–40°C to +85°C

74LVCH16374A DL

48-Pin Plastic TSSOP Type II

–40°C to +85°C

74LVCH16374A DGG

TYPICAL

3.8

150

5.0

30

UNIT

ns

MHz

pF

pF

NORTH AMERICA

VC16374A DL

VC16374A DGG

VCH16374A DL

VCH16374A DGG

DWG NUMBER

SOT370-1

SOT362-1

SOT370-1

SOT362-1

1998 Mar 17

2

853-2028 19111

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