TSC87C52-L16IHD 查看數據表（PDF） - Temic Semiconductors
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TSC87C52-L16IHD Datasheet PDF : 24 Pages
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TSC87C52
External Data Memory Read Cycle
ALE
TLLDV
TWHLH
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR–P2
TLLWL
TRLRH
TLLAX
A0–A7
TAVWL
TAVDV
TRLAZ
ADDRESS A8–A15 OR SFR P2
TRHDX
DATA IN
TRHDZ
Serial Port Timing – Shift Register Mode
Symbol
TXLXL
TQVHX
TXHQX
TXHDX
TXHDV
Parameter
Serial port clock cycle time
Output data set–up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
0 to 12MHz
Min
Max
12TCLCL
10TCLCL–133
2TCLCL–117
0
10TCLCL–133
Units
ns
ns
ns
ns
ns
Shift Register Timing Waveforms
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE to SBUF
INPUT DATA
CLEAR RI
0
1
2
3
4
5
6
7
8
TXLXL
TQVXH
0
TXHQX
1
2
TXHDV
TXHDX
VALID
VALID
VALID
3
VALID
4
VALID
5
VALID
6
7
SET TI
VALID
VALID
SET RI
20
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
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