UPD4990AG 查看數據表（PDF） - NEC => Renesas Technology

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UPD4990AG

SERIAL I/O CALENDAR & CLOCK CMOS LSI

NEC => Renesas Technology 

OE

CLK

DATA

IN

XTAL

XTAL

C2

C1

C0

CS

STB

CLK

CS

COMMAND

Register

CLK RH

C3' C2' C1' C0'

48 Bit Shift Register

MPX

1 Hz

OSC

Select signal

generator circuit

C3'

C2'

C1'

C0'

YEAR

PS

DAY HOUR MIN SEC

Time counter

15 Stage Binary Divider

1/215

64 Hz

TEST

1 Hz

1/26

SEC

STOP

RESET

MPX

N-ch

OPEN DRAIN

DATA

OUT

TP

MPX : Multiplexer

PS : Preset

D/W : Day of the Week

CS : Chip Select

TP : Timing Pulse

RH : Register Hold

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