WED3DL3216V10BI 查看數據表（PDF） - White Electronic Designs Corporation
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WED3DL3216V10BI Datasheet PDF : 27 Pages
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White Electronic Designs
WED3DL3216V
Current
State
Refreshing
Mode
Register
Accessing
CURRENT STATE TRUTH TABLE (cont.)
Command
CE# RAS# CAS# WE# BA0-1
A0-A12
Action
Description
Notes
L
L
L
L
OP Code
Mode Register Set ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H BA Row Address Bank Activate
ILLEGAL
L
H
L
L
BA
Column Write
ILLEGAL
L
H
L
H BA
Column Read
ILLEGAL
L
H
H
L
X
X
Burst Termination No Operation; Idle after tRC
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
OP Code
Mode Register Set ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H BA Row Address Bank Activate
ILLEGAL
L
H
L
L
BA
Column Write
ILLEGAL
L
H
L
H BA
Column Read
ILLEGAL
L
H
H
L
X
X
Burst Termination ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is
being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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