M61311SP 查看數據表（PDF） - Renesas Electronics

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M61311SP

l2C BUS Controlled Video Pre-amp for High Resolution Color Display

Renesas Electronics 

M61311SP/M61316SP

VthBLK OSD BLK Input Threshold Voltage

Confirm that output signal is being blanked by the SG6 at the time.

Decrease the SG6 input level gradually from 5.0 VP-P, monitoring the output. Measure the top level of SG6 when the

blanking period is disappeared. And increase the SG6 input level gradually from 0 VP-P. Measure the top level of SG6

when the blanking period is appeared. The measured value is called VthBLK.

HBLK1 Retrace BLK Characteristics1

Measure the bottom voltage at amplitude of OUT (26, 28, 30). The measured value is called HBLK1.

HBLK2 Retrace BLK Characteristics2

Measuring condition and procedure are the same as described in HBLK1.

HBLK3 Retrace BLK Characteristics3

Measuring condition and procedure are the same as described in HBLK1.

VthHBLK Retrace BLK Input Threshold Voltage

Decrease the SG7 input level gradually from 5.0 VP-P, monitoring the output. Measure the top level of SG7 when the

output is disappeared. And increase the SG7 input level gradually from 0 VP-P. Measure the top level of SG7 when the

output is appeared. The measured value is called VthHBLK.

SS-NV SOG Input Maximum Noise Voltage

When SG4 is all black (no video), the sync's amplitude of SG4 gradually from 0 VP-P to 0.02 VP-P. No pulse output

permitted.

SS-SV SOG Minimum Input Voltage

When SG4 is all white or all black, the sync's amplitude of SG4 gradually from 0.2 VP-P to 0.3 VP-P. Positive pulse has

occurred to Sync Sepa OUT.

VSH Sync Output High level

Measure the high voltage at Sync Sepa OUT. The measured value is treated as VSH.

VSL Sync Output Low Level

Measure the low voltage at Sync Sepa OUT. The measured value is treated as VSL.

TDS-F Sync Output Delay Time1

Sync Sepa OUT becomes high with sink part of SG4.

Measure the time needed for the front edge of SG4 Sync to fall from 50% and for SyncOUT to rise from 50% with an

active probe. The measured value is called TDS-F.

TDS-R Sync Output Delay Time2

Sync Sepa OUT becomes high with sink part of SG4.

Measure the time needed for the rear edge of SG4 Sync to rise from 50% and for SyncOUT to fall from 50% with an

active probe. The measured value is called TDS-R.

SG4

Sync Sepa OUT

Sync (50%)

TDS-F

Pedestal voltage

(50%)

TDS-R

REJ03F0199-0201 Rev.2.01 Mar 31, 2008

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