MAX3873A(2003) 查看數據表（PDF） - Maxim Integrated

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MAX3873A
(Rev.:2003)

Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery and Data-Retiming IC

Maxim Integrated 

PIN

10

11

12

13

14

15

16

17, 20

18

19

EP

Low-Power, Compact 2.5Gbps or 2.7Gbps

Clock-Recovery and Data-Retiming IC

NAME

SCLKEN

SCLKO-

SCLKO+

VCC_BUF

SDO-

SDO+

LOL

GND

FIL-

FIL+

Exposed Pad

Pin Description (continued)

FUNCTION

Clock Output Enable, TTL Input. When SCLKEN = open or SCLKEN = high, the clock outputs

(SCLKO±) are enabled. When SCLKEN = low, the clock outputs are disabled and SCLKO± = VCC.

Negative Clock Output, CML. This output can be disabled by setting SCLKEN to low.

Positive Clock Output, CML. This output can be disabled by setting SCLKEN to low.

3.3V CML Output Buffer Supply Voltage

Negative Data Output, CML

Positive Data Output, CML

Loss-of-Lock Output, TTL (Active Low). The LOL output indicates a PLL lock failure.

Supply Ground

Negative PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.

Positive PLL Loop Filter Connection. Connect a 0.022µF capacitor between FIL+ and FIL-.

Ground. The exposed pad must be soldered to the circuit board ground for proper electrical and

thermal operation.

Detailed Description

The MAX3873A consists of a fully integrated phase-

locked loop (PLL), input amplifier, and CML output

buffers (Figure 5). The PLL consists of a phase/fre-

quency detector, a loop filter, and a voltage-controlled

oscillator (VCO).

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully differential signal architecture and low-noise

design techniques.

VCC

GND

FIL+ FIL- RATESET

MAX3873A

SDI+

AMP

SDI-

PHASE AND

FREQUENCY

DETECTOR

SDO+

AMP

SDO-

MODE

LOOP

FILTER

I

VCO

Q

SCLKO+

AMP

SCLKO-

SCLKEN

LOL

FASTRACK

Figure 5. Functional Diagram

Input Amplifier

The input amplifier provides internal 50Ω line termina-

tions and can accept a differential input amplitude from

50mVP-P to 1600mVP-P. The structure of the input

amplifier is shown in Figure 9.

Phase Detector

The phase detector incorporated in the MAX3873A pro-

duces a voltage proportional to the phase difference

between the incoming data and the internal clock.

Because of its feedback nature, the PLL drives the

error voltage to zero, aligning the recovered clock to

the center of the incoming data eye for retiming.

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during startup conditions. The frequency

difference between the received data and the VCO

clock is derived by sampling the VCO outputs on each

edge of the data input signal. The FD drives the VCO

until the frequency difference is reduced to zero. Once

frequency acquisition is complete, the FD returns to a

neutral state.

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. An external capacitor, CF,

is required to set the PLL damping ratio. See the

Design Procedure section for guidelines on selecting

this capacitor.

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