S3C2800 查看數據表（PDF） - Samsung
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S3C2800 Datasheet PDF : 22 Pages
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S3C2800
32-Bit RISC
Microprocessor
Data Sheet
OVERVIEW
SAMSUNG's S3C2800 32-bit RISC microprocessor is designed to provide a cost-effective and high-performance
micro-controller solution for general applications. The S3C2800 features the following integrated on-chip support
to help design a system a low cost: 16KB I/D caches, 2-ch UART with handshake, 4-ch DMA, memory controller,
3-ch timer, GPIO (General-Purpose Input/Output) ports, RTC (Real Time Clock), 2-ch IIC-BUS interface, and a
built-in PLL for system clock.
Based on ARM920T core, the S3C2800 is developed using 0.18 um CMOS standard cells and a memory
compiler. Its simple, elegant, and fully static low-power design is particularly suitable for both cost-sensitive and
power-sensitive applications. The 32-bit ARM920T RISC processor core (220Mips @200MHz), designed by
Advanced RISC Machines, Ltd., provides architectural enhancements such as the Thumb de-compressor, a 32-
bit hardware multiplier, and an on-chip ICE debug support. Also, the S3C2800 features the Harvard BUS
architecture for efficient data/instruction transfers.
By integrating various common system peripherals, the S3C2800 minimizes the overall system cost and
eliminates the need to configure additional components. The integrated on-chip functions are summarized as
follows :
• PCI BUS interface (32-bit, up to 66MHz).
• 1.8V static ARM920T CPU core with 16KB I/D (Instruction/Data) cache. (Harvard bus architecture up to
200MHz).
• External memory controller. (FP/EDO/SDRAM control, Chip select logic).
• 4-ch general DMAs with external request pins.
• 2-ch UART with handshake (IRDA1.0, 16-byte FIFO), Modem Interface.
• 2-ch multi-master IIC-BUS controller.
• 3-ch 16-bit timer.
• 16-bit Watchdog timer.
• 44 general-purpose GPIO ports including 8 external interrupt source.
• Power management: Normal, Slow, and Idle modes.
• RTC with calendar function.
• On-chip PLL clock generator.
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