Electrical Characteristics
VI - VO = 5 V, IO = 0.1 A, 0°C ≤ TJ ≤ +125°C, PDMAX = 7.5 W, unless otherwise specified.
Symbol
Rline
Rload
IADJ
ΔIADJ
VREF
STT
IL(MIN)
IO(MAX)
eN
RR
Parameter
Conditions
Line Regulation(3)
Load Regulation(3)
Adjustment Pin Current
TA = +25°C, 3 V ≤ VI −VO ≤ 40 V
3 V ≤ VI −VO ≤ 40 V
TA = +25°C, 10 mA ≤ IO ≤ 0.5 A,
VO ≤ 5 V
TA = +25°C, 10 mA ≤ IO ≤ 0.5 A,
VO ≥ 5 V
10 mA ≤ IO ≤ 0.5 A, VO ≤ 5 V
10 mA ≤ IO ≤ 0.5 A, VO ≥ 5V
-
Adjustment Pin Current Change
Reference Voltage
Temperature Stability
Minimum Load Current to
Maintain Regulation
3 V ≤ VI - VO ≤ 40 V,
10 mA ≤ IO ≤ 0.5 A, PD < PDMAX
3 V < VI - VO < 40 V,
10 mA ≤ IO ≤ 0.5 A, PD < PDMAX
TJ = 0°C to +125°C
VI - VO = 40 V
Maximum Output Current
RMS Noise, % of VOUT
Ripple Rejection
VI - VO ≤ 15 V, PD < PDMAX
VI - VO = 40 V
PD < PDMAX, TA = +25°C
TA = +25°C, 10 Hz < f < 10 kHz
VO = 10 V, f = 120 Hz,
without CADJ
VO = 10 V, f = 120 Hz,
CADJ = 10 μF(4)
Min.
1.20
0.5
0.15
66
ST
Long-Term Stability
TJ = +125°C, 1000 Hours
Typ.
0.01
0.02
5
0.1
20
0.3
50
0.2
1.25
0.7
3.5
0.9
0.25
0.003
65
80
0.3
Max.
0.04
0.07
25
Unit
%/ V
mV
0.5 %/VO
70
mV
1.5 %/VO
100
μA
5.0
μA
1.30
V
%/VO
10.0 mA
A
%/VO
dB
1
%/
1000Hrs
Notes:
3. Load and Line regulation are specified at constant junction temperature. Change in VO due to heating effects must
be taken into account separately. Pulse testing with low duty cycle is used.
4. CADJ, when used, is connected between the adjustment pin and ground.
© 2003 Fairchild Semiconductor Corporation
LM317M Rev. 1.1.0
3
www.fairchildsemi.com