A4988 查看數據表（PDF） - Allegro MicroSystems

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A4988

DMOS Microstepping Driver with Translator and Overcurrent Protection / 28-contact QFN

Allegro MicroSystems 

A4988

DMOS Microstepping Driver with Translator

And Overcurrent Protection

input sequences the translator and advances the motor one incre-

ment. The translator controls the input to the DACs and the direc-

tion of current flow in each winding. The size of the increment is

determined by the combined state of the MSx inputs.

Direction Input (DIR). This determines the direction of rota-

tion of the motor. Changes to this input do not take effect until the

next STEP rising edge.

Internal PWM Current Control. Each full-bridge is con-

trolled by a fixed off-time PWM current control circuit that limits

the load current to a desired value, ITRIP . Initially, a diagonal pair

of source and sink FET outputs are enabled and current flows

through the motor winding and the current sense resistor, RSx.

When the voltage across RSx equals the DAC output voltage, the

current sense comparator resets the PWM latch. The latch then

turns off the appropriate source driver and initiates a fixed off

time decay mode

The maximum value of current limiting is set by the selection of

RSx and the voltage at the VREF pin. The transconductance func-

tion is approximated by the maximum value of current limiting,

ITripMAX (A), which is set by

▪ ROSC through a resistor to ground — off-time is determined

by the following formula, the decay mode is automatic Mixed

decay for all step modes except full step whic is set to slow

decay.

tOFF ≈ ROSC ⁄  825

Where tOFF is in µs.

Blanking. This function blanks the output of the current sense

comparators when the outputs are switched by the internal current

control circuitry. The comparator outputs are blanked to prevent

false overcurrent detection due to reverse recovery currents of the

clamp diodes, and switching transients related to the capacitance

of the load. The blank time, tBLANK (µs), is approximately

tBLANK ≈ 1 µs

Shorted-Load and Short-to-Ground Protection.

If the motor leads are shorted together, or if one of the leads is

shorted to ground, the driver will protect itself by sensing the

overcurrent event and disabling the driver that is shorted, protect-

ing the device from damage. In the case of a short-to-ground, the

device will remain disabled (latched) until the S¯ ¯L¯ ¯E¯ ¯E¯ ¯P input goes

high or VDD power is removed. A short-to-ground overcurrent

event is shown in Figure 4.

× ITripMAX = VREF / ( 8   RS)

where RS is the resistance of the sense resistor (Ω) and VREF is

the input voltage on the REF pin (V).

The DAC output reduces the VREF output to the current sense

comparator in precise steps, such that

× Itrip = (%ITripMAX / 100) ITripMAX

When the two outputs are shorted together, the current path is

through the sense resistor. After the blanking time (≈1 µs) expires,

the sense resistor voltage is exceeding its trip value, due to the

overcurrent condition that exists. This causes the driver to go into

a fixed off-time cycle. After the fixed off-time expires the driver

turns on again and the process repeats. In this condition the driver

is completely protected against overcurrent events, but the short

is repetitive with a period equal to the fixed off-time of the driver.

This condition is shown in Figure 5.

(See Table 2 for %ITripMAX at each step.)

It is critical that the maximum rating (0.5 V) on the SENSE1 and

SENSE2 pins is not exceeded.

Fixed Off-Time. The internal PWM current control circuitry

uses a one-shot circuit to control the duration of time that the

DMOS FETs remain off. The off-time, tOFF, is determined by the

ROSC terminal. The ROSC terminal has three settings:

▪ ROSC tied to VDD — off-time internally set to 30 µs, decay

mode is automatic Mixed decay except when in full step where

decay mode is set to Slow decay

▪ ROSC tied directly to ground — off-time internally set to

30 µs, current decay is set to Mixed decay for both increasing

and decreasing currents for all step modes.

During a shorted load event it is normal to observe both a posi-

tive and negative current spike as shown in Figure 3, due to the

direction change implemented by the Mixed decay feature. This

is shown in Figure 6. In both instances the overcurrent circuitry is

protecting the driver and prevents damage to the device.

Charge Pump (CP1 and CP2). The charge pump is used to

generate a gate supply greater than that of VBB for driving the

source-side FET gates. A 0.1 µF ceramic capacitor, should be

connected between CP1 and CP2. In addition, a 0.1 µF ceramic

capacitor is required between VCP and VBB, to act as a reservoir

for operating the high-side FET gates.

Capacitor values should be Class 2 dielectric ±15% maximum,

or tolerance R, according to EIA (Electronic Industries Alliance)

specifications.

Allegro MicroSystems, LLC

9

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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